Intel is hiring a Physical Design Execution Lead for a faraway function. This function involves overseeing and executing bodily design responsibilities, participating with cross-useful teams to meet undertaking goals, and making sure of the fine and performance of chip designs. The ideal candidate may have strong experience in bodily design flows, EDA tools, and layout for manufacturability (DFM). The position offers bendy surroundings and aggressive advantages.
- Job Title: Physical Design Execution Lead
- Salary: Not Disclosed
- Location: Bengaluru, Karnataka
- Company: Intel
- Qualifications: Graduate
- Experience: 8 to 12 years
ABOUT INTEL
Intel Corporation is a worldwide leader in semiconductor innovation, acknowledged for designing and producing different microprocessors, chipsets, and associated technologies. Founded in 1968, Intel pioneered the improvement of the microprocessor, fueling the growth of the private computer industry. Today, Intel’s merchandise strengthens an extensive range of devices, from computer systems and facts facilities to artificial intelligence, self-sustaining vehicles, and IoT applications.
The enterprise operates on a global scale, with research and improvement facilities, manufacturing centers, and places of work worldwide. Intel is committed to driving technological improvements, sustainability, and inclusion, with a focal point on innovation in areas like 5G, cloud computing, and subsequent-era semiconductors. Its leadership in manner technology and chip production has positioned Intel at the leading edge of the digital transformation. With a sturdy corporate tradition, Intel maintains to draw top skills and fosters a collaborative, inclusive environment for innovation.
Job Overview:
The Physical Design Execution Lead performs a vital function in riding the successful execution of the bodily layout (PD) method for included circuits (ICs) from idea to final tape-out. This function requires deep information on the bodily layout float, including floorplanning, placement, routing, timing closure, power optimization, and DRC/LVS signal-off. The position includes leading a team of engineers whilst taking part with go-functional businesses to make certain the physical design meets overall performance, strength, and location (PPA) goals.
Key Responsibilities For Physical Design Execution Lead (Remote Work):
- Leadership and Team Management: Led and mentored a crew of bodily design engineers, making sure of the powerful execution of the PD obligations and assembly assignment deadlines. Guide high-quality practices, methodologies, and tool utilization.
- Physical Design Execution: Oversee and control the quit-to-quit bodily layout process, along with floorplanning, placement, routing, clock tree synthesis, and static timing evaluation. Ensure designs meet important specs for strength, overall performance, and location.
- Tool and Methodology Selection: Work with layout tools like Cadence, Synopsys, or Mentor Graphics to put into effect efficient layout flows. Continuously examine and advocate gear, technologies, and methodologies for boosting layout high quality, and productiveness.
- Cross-Functional Collaboration: Collaborate intently with the front-give-upp design groups (RTL designers), verification teams, and production engineers to ensure seamless handoff between layout stages. Provide comments and guidelines for enhancing the layout technique.
- Timing Closure and Sign-Off: Ensure timing closure across a couple of corners, examine timing violations, and lead efforts to solve essential timing paths. Drive the system for final signal-offs, consisting of DRC (Design Rule Check) and LVS (Layout vs. Schematic).
- Quality Assurance and Optimization: Ensure the bodily design is optimized for manufacturability and yield. Lead efforts in optimizing designs for power, performance, and vicinity (PPA), minimizing place, decreasing strength intake, and enhancing vital performance.
- Remote Team Management: Manage a dispensed group of engineers efficaciously by imparting clean conversation, defining milestones, and making sure of efficient virtual collaboration.
Qualifications:
- Bachelor’s or Master’s diploma in Electrical Engineering or related area.
- Extensive experience in physical design for ASICs, FPGAs, or SoCs, with knowledge in format, routing, timing, and optimization.
- Strong proficiency with EDA equipment (Cadence, Synopsys, Mentor Graphics) and scripting languages (e.g., TCL, Python).
- Proven enjoy in leading teams, with notable communique and undertaking management talents.
- Ability to work independently and thrive in a far off, fast-paced surroundings.
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