NVIDIA Hiring Formal Verification Engineer Job in Bengaluru | Apply Now

A Formal Verification Engineer ensures the correctness of virtual designs and the usage of mathematical strategies. Responsibilities encompass developing and applying formal verification methodologies, developing homes for verification, debugging layout troubles, and taking part in layout groups. Proficiency in formal verification gear and sturdy analytical talents are critical for this function in ensuring sturdy and dependable hardware designs.

Job Role: Formal Verification Engineer

Salary: ₹18.8 Lakhs per year

Location: Bengaluru, Karnataka

Company: NVIDIA

Qualification: B.Tech./ M.Tech

Experience: 2+year

About Company:

NVIDIA Corporation, based in 1993 and based in Santa Clara, California, is a worldwide chief in GPU (images processing unit) layout. It pioneered the GPU-pushed deep studying and synthetic intelligence revolution, making good-sized improvements in gaming, expert visualization, data facilities, and automobile industries. NVIDIA’s CUDA parallel computing platform and AI technologies are pivotal in accelerating scientific discoveries and powering autonomous motors. Known for its GeForce, Quadro, and Tesla brands, NVIDIA continues to force innovation in GPU computing, focusing on advancing AI, robotics, and self-sufficient structures. As for recent traits, it has multiplied its reach into software program-described networking and AI-powered healthcare solutions.

Role Overview:

NVIDIA is hiring a Formal Verification Engineer in Bengaluru to verify SoC and GPU designs. This full-time position involves participating in layout and structure groups, growing tremendous test plans, and growing verification flows. Ideal candidates have a B.Tech./M.Tech with 2+ years of enjoy in formal verification, hardware design, and debugging. Strong conversation abilties and scripting expertise are a plus. NVIDIA gives competitive salaries and exceptional advantages, and values variety and equal opportunity.

Roles and Obligations Of Formal Verification Engineer Job at NVIDIA:

Specification Analysis:

Analyzing design specs to discover crucial houses and behaviors that want formal verification. This entails know-how of complex hardware/software program necessities.

Formal Verification Planning:

Creating a verification plan outlining the scope, goals, and methodology for formal verification. This includes choosing suitable gear and techniques based on undertaking requirements.

Assertion and Property Development:

Writing assertions and homes in formal verification languages (e.g., SystemVerilog Assertions, PSL) to seize layout intent and confirm correctness beneath all conditions.

Formal Verification Execution:

Running formal verification gear to exhaustively check layout houses and uncover ability insects or layout flaws early in the development cycle.

Debugging and Analysis:

Analyzing counterexamples and verification effects to debug design issues and collaborate with design and verification groups to solve them efficiently.

Skills Required For Formal Verification Engineer:

Formal Verification Techniques:

Proficiency in formal techniques inclusive of model checking, theorem proving, and formal belongings verification. This consists of knowledge of formal languages like temporal logics (e.g., PSL, SVA) and formal verification gear (e.g., Cadence JasperGold, Synopsys VC Formal).

Hardware Description Languages (HDL):

Stronghold’s close of HDLs like Verilog or VHDL is important for understanding and modeling digital designs. This understanding facilitates in development of effective formal verification environments and knowledge layout specifications.

Problem-Solving and Debugging:

Ability to identify complicated design troubles and debug them efficiently through the usage of formal verification tools and methodologies. This involves logical reasoning and deep expertise in digital circuits and systems.

Scripting and Automation:

Proficiency in scripting languages like Python, Perl, or TCL to automate obligations consisting of test case generation, tool scripting, and outcomes evaluation. Automation competencies are essential for managing big-scale formal verification projects successfully.

Communication and Collaboration:

Strong verbal exchange capabilities to interact with layout teams, explain findings, and collaborate on resolving verification troubles. This consists of documenting verification plans, and outcomes, and offering clean comments to design groups.

Qualification:

Qualified with a B.Tech./M.Tech or equivalent, and over 2 years of relevant experience. Proficient in hardware micro-architecture and design, with expertise in formal verification technologies and complexity reduction techniques. Experienced in formal property verification for complex units, adept at creating high-quality test plans, building formal test benches, and root-causing counter-examples.